Senior Front End ASIC SoC Design Engineer
We are seeking a seasoned Front-end SoC Design Engineer for our ASIC business unit.
The primary responsibilities include but are not limited to:
- Support customer's design through all phases of ASIC execution.
- Collaborate very closely with the architecture and FW teams, IP assessment/selection, define subsystem and performance analysis.
- Responsible for creating SoC/CPU subsystem design specification, RTL coding, SoC integration, block level verification and assist in top level verification.
- Focus on design execution by performing synthesis and timing closure tasks to ensure the design meets product performance requirements.
- Lead and participate in key activities and phase reviews to ensure project execution to committed project timeline and product performance requirements
Requirements for this position:
- Bachelor?s Degree in EE, Masters preferred.
- 15+ years of successful design experience, including:
- 10+ years of Micro Architecture/Resource tradeoff, RTL design using Verilog/System Verilog, SoC Integration CDC, LINT.
- 5+ years of experience performing synthesis, timing analysis/timing closure, formal verification/LEC, DFT, ATE.
- Requires an excellent understanding of ASIC design and manufacturing flows targeting 28 nm and below with proven track record of working on high performance SoC/ASIC design from concept to tape-out to bring-up.
- Proven expertise in one or more of the following domains: high speed ARM interconnect or memory subsystems such as CCI, AXI, ACE, AHB and APB
- Prior Experiencewith A53, A72, A73 ARM cores and Architecture
- Familiarity with revision control concepts and tools (e.g. Subversion)
- Experience with Perl, Tcl, Python, Unix scripting.
- Teamwork, dedication, strong communications and interpersonal skills
- Some travel ~30%
- Experience in 1 or more area from Media standards, image processing and video standards (JPEG, MPEG, H.264.H.265)
- Prior experiencewith Interface like MIPI, PCIe, USB, LPDDR3/4, Peripherals (I2C, I2S, SPI, GPIO etc.) is desired.
- ASIC Design Verification experience in block level as well as subsystem level verification using UVM, gate level verification, power verification is a plus
- prior experienceworking with low power design, UPF integration, boot-up, power-cycling, HW/FW interaction verification is highly desirable
- Ability to lead with varied goals and objectives to achieve business unit?s direction and purpose.
- Self-motivated, and able to prioritize work assignments.
All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, genetics, disability, age, or veteran status.