About the Team:
Join the growing Encore Semi Front-End Development team to collaborate with customers to design, and verify large FPGA designs implementing control logic for systems which operate in harsh and remote environments. Building on your background of Functional Verification, you would join a team verifying multiple features at the unit and full-chip.
About the Project:
As a senior member of a complex FPGA development team, you would be responsible for driving the Design Verification of either blocks (units) or full-chip elements of a complete FPGA design. You will leverage your SV/UVM experience assisting the current verification team to shift into fuller deployment of this methodology while developing Verification plans, creating environments and executing tests to stress the design. One of the special focuses for design are requirements for long-term operation in harsh environments. These requirements drive additional design elements (such as additional error detection, correction and redundancy) and add interesting requirements to demonstrating extreme functional correctness which increases the challenge and complexity of demonstrating a highly functional design ready for production. If you have SV / UVM Verification experience with environments, stimulus, random stress and deploying a coverage-based approach, joining the Encore Semi Verification team could be for you.
• Functional (Design) Verification at the block or SOC / “Full-Chip” level using simulation models. Experience should include creating Verification Plans from the Microarchitecture Specifications and ability to understand the RTL
• SV/UVM methodology expertise to create Verification environments and drive Functional Verification including test / stimulus creation and debugging failures to root cause
• Computer architecture background to enable flexibility to validate multiple different areas of the design
• 7+ years of Design Verification experience including working with RTL Developers
• MUST be US Citizen
• Experience with IP blocks such as Serial RapidIO (sRIO), DDR3, memories, internal interconnects, SerDes, ECC, TMR
• Experience with Verification for FPGA designs (esp using Xilinx FPGAs) is a positive in addition to DV for SOC / ASICs
• Experience using Mentor Graphics tools including simulation (Questasim) and emulation (Veloce)
• Required: Bachelor's, Electrical Engineering
• Preferred: Master's, Electrical Engineering