Who We Are:
Ball Aerospace leads the way in designing, developing and manufacturing innovative aerospace systems. We take on some of the most complex and exciting challenges in the universe--from space and Earth science to national security and intelligence programs.
We produce spacecraft, instruments and sensors, RF and microwave technologies, data exploitation solutions, and a variety of advanced aerospace technologies and products. In addition, we pioneered the development of the commercial remote sensing market, producing spacecraft and imaging systems that helped spawn a market-driven demand for imagery.
Our success is built on more than products or systems. Our team of more than 3,000 engineers, scientists, technicians and support staff drives all the achievements at Ball Aerospace. Whether contributing to a better understanding of the universe or helping keep our nation safe, our people bring their diverse backgrounds, perspectives and skills together to achieve a common mission.
Senior FPGA Verification Engineer
Candidate will be responsible for FPGA/ASIC verification of space-based electronic systems using simulation and verification environments to prove the functional correctness of FPGA/ASIC designs.
What You'll Do:
- Verify designs (including SOC architectures utilizing soft-core processors, digital filters, image processing algorithms, and communication interfaces/protocols), design and implement test benches and test plans for both chip-level and system level environments, and create reusable verification environments that can be used across multiple projects.
- Work in System Verilog/UVM environment and be responsible for generating FPGA verification plan, verification matrix and developing verification environments for test and verification of flight FPGA code/modules.
- Work collaboratively and in tandem with system architects, FPGA design engineers and embedded software engineers.
- Maintain a regular and predictable work schedule.
- Establish and maintain effective working relationships within the department, the Strategic Business Unit/Strategic Support Unit and the Company. Interact appropriately with others in order to maintain a positive and productive work environment.
- Perform other duties as necessary.
What You'll Need:
- BS degree or higher in Engineering or a related technical field is required plus 8 or more years related experience.
- Each higher-level degree, i.e., Master’s Degree or Ph.D., may substitute for two years of experience. Related technical experience may be considered in lieu of education. Degreemust be from a university, college, or school which is accredited by an agency recognized by the US Secretary of Education, US Department of Education.
- Strong FPGA/ASIC Verification development methodology.
- Experience with System Verilog and UVM, and familiarity with electronic circuit design and electronic systems.
- A solid understanding of object-oriented concepts and experience designing class-basedconstrained random test benches.
- Experience with coverage writing (including coverpoints, crosses), coverage collection and improving coverage of the design under test.
- Experience with VHDL Modelsim/Questa simulator is a plus.
- Experience in C++ object-oriented programming is a plus.
- Knowledge and experience with Windows, Linux and scripting languages (e.g. Ruby, Python, TCL) is a plus.
- Experience in documentation and verification of high-speed digital electronics, FPGAs, and embedded processor systems is desired.
- Ability to develop specifications, cost, schedule, and resource requirements for FPGA or ASIC verification plans.
- Strong verbal and written communication skills, as well as strong presentation skills.
- Work is performed in an office, laboratory, production floor, or clean room, outdoors or remote research environment.
- May occasionally work in production work centers where use of protective equipment and gear is required.
- May access other facilities in various weather conditions.
- Travel and local commute between Ball campuses and other possible non-Ball locations may be required.