Our team is looking for innovative and passionate engineers to help create high performance communication products, such as software-defined radios and data links, and computer graphics hardware. As part of our team, you’ll have the ability to significantly contribute to the creation of our newest products.
Sr Electrical Engineer – FPGA & ASIC Design Solutions – Government Systems
Become part of the growing Government Systems Engineering FPGA & ASIC Design Solutions team. As an engineer in this organization, you will be a member of an experienced, dynamic design group employing best practice design methodologies supporting our next generation of Communication Products, and image generators in addition to numerous products corporate-wide.
This position is for an experienced and motivated Senior Electrical or Computer engineering experienced candidate to be involved in the design, implementation, verification and integration of a wide variety of high-performance digital ASICs and FPGAs applied to signal processing and information assurance applications.
* Requirements capture, ASIC / FPGA digitalarchitecture and design using RTL, timing analysis and closure, verification, and system integration
* RTL coding and simulation in VHDL or Verilog
* Testbench development for the verification of RTL blocks using VHDL or SystemVerilog
* Recommend new tools and practices for continuous improvement in the group’s ASIC / FPGA design flow
This position is located in Salt Lake City, UT. A comprehensive relocation package is available for qualified candidates.
Must Have Requirements:
*Bachelor’s degree in a Science, Technology, Engineering or Math (STEM) discipline
* Must possess or be eligible for obtaining a U.S. DoD Secret Clearance. U.S. Citizenship is required. Candidate selected will be subject to a government securityinvestigation/re-instatement and must meet eligibility requirements.
This position requires these skills and abilities:
* RTL coding and simulation in VHDL or Verilog OR Testbench development for the verification of RTL blocks using VHDL or SystemVerilog
* Proficiency using ASIC and/or FPGA simulation and synthesis tools (e.g. Modelsim, Synopsys, FPGA-specific tools)
* Familiarity with revision control concepts and tools (e.g. Subversion)
* Ability to work with minimal supervision, part of a team of engineers with a variety of skills and backgrounds, matrixed into projects with aggressive schedules and frequent milestones
* Strong oral and written communication skills and the ability to document and present one’s work and status
Desired skills of a successful candidate:
*Digitalcircuitarchitecture, design, resource tradeoffs, timing analysis and timing closure
* Familiarity with best practice chip-level verification techniques and languages (e.g. constrained random, functional coverage, SystemVerilog)
* ASIC / FPGA lab validation with advanced lab equipment
* Design for Test (DFT) and manufacturability issues
*Experience with Unix, scripting, C/C++, and/or Perl
Requisition ID: 6952