Senior DFT Engineer

8 - 10 years experience  •  Business Services

Salary depends on experience
Posted on 02/19/18
8 - 10 years experience
Business Services
Salary depends on experience
Posted on 02/19/18

Company Description

NXP Semiconductors enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better and safer. As the world leader in secure connectivity solutions for embedded applications, we are driving innovation in the secure connected vehicle, end-to-end security & privacy and smart connected solutions markets.

Business Unit Description

NXP’s Automotive business unit offers sensor and processing technology that drives all aspects of the secure connected cars of today and the autonomous cars of tomorrow.

Job Summary:

  • Develop, document and implement DFT methodologies for the Automotive and Processors Business unit.
  • Memory BIST Algorithm Development, Support & Documentation
  • Define, support and document JTAG implementation standards and methods
  • Define, support and document DFT strategies for IP and transceivers
  • Develop, support and document strategies for delay fault testing
  •  Define and drive DFT software tool strategy, both industry standard and internally developed
  •  Interface with 3rd party vendors and CAD department
  •  Contribute to future software vendor selection
  •  Define internal/custom software & script needs and work with CAD on implementation
  •  Ownership for all aspects of the DFT strategies for the Business Units Product Lines

Job Qualifications:

  • 8+ years in SoC Design
  • 8+ years in DFT Methodology/Implementation
  • 8+ years total Industry (SoC) Experience
  • Memory BIST Algorithm development and implementation
  • At-speed, Diagnostic for Failure Analysis
  • JTAG Boundry Scan Design & implementation
  • IC Parametric test methods and implementation
  • Transition & Path delay testing
  • Scan testing methods
  • Low pin-count test methods
  • IP test methods & implementation
  • PLL, DLL, A/D, D/A, Transceivers: LVDS, PCI-e, XAUI, USB, SPI
  • Experience with industry standard DFT tools such as Synopsys or Mentor (Synopsys preferred)
  • Excellent written and verbal communication skills in English
  • Ability to travel domestically and internationally as needed (~15-20%)
  • Proven track record in SoC DFT methodology development
    R-10008385
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