Senior DFT Engineer

8 - 10 years experience  •  Business Services

Salary depends on experience
Posted on 02/19/18
8 - 10 years experience
Business Services
Salary depends on experience
Posted on 02/19/18

Company Description

NXP Semiconductors enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better and safer. As the world leader in secure connectivity solutions for embedded applications, we are driving innovation in the secure connected vehicle, end-to-end security & privacy and smart connected solutions markets.

Business Unit Description

NXP’s Automotive business unit offers sensor and processing technology that drives all aspects of the secure connected cars of today and the autonomous cars of tomorrow.

Job Summary

The Senior DFT Engineering role will involve many aspects of Test and DFT and will be a lead member in the R&D Design Quality group.  A strong ability to reduce problem space and to root-cause problems from corner case failures and then to anticipate new protentional failure modes is required. Engagement and collaboration across functional teams is a key aspect of this role. Strong technical, communication, and consensus building skills will be required. Strong ability to clearly articulate the root-cause of a defect and provide recommendations to systematically address the problem is needed.  Capability to interface with customer is desired. The ideal candidate will partner with local and global SoC and IP developers to drive best practices with a target of ongoing productivity improvement. A “zero-defect” mindset is a key enabler.  Responsibilities encompass the enhancement of DFT test bench, debugging failures, assessing test coverage gaps in existing products.

Job Qualifications

  • 8+ years in SoC Design
  • 8+ years in DFT Methodology/Implementation
  • 8+ years total Industry (SoC) Experience
  • Memory BIST Algorithm development and implementation
  • At-speed, Diagnostic for Failure Analysis
  • JTAG Boundary Scan Design & implementation
  • IC Parametric test methods and implementation
  • Transition & Path delay testing
  • Scan testing methods
  • Low pin-count test methods
  • IP test methods & implementation
  • PLL, DLL, A/D, D/A, Transceivers: LVDS, PCI-e, XAUI, USB, SPI
  • Experience with industry standard DFT tools such as Synopsys or Mentor
  • Excellent written and verbal communication skills in English
  • Ability to travel domestically and internationally as needed (~15%)
  • Proven track record in SoC DFT methodology development
  • In-depth direct experience in DFT methods and implementation required
  • Excellent debug skills required

Education

BSEE / MSEE / PhD plus 8+ years’ experience in Semiconductor industry.

  • R-10008627
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