Job Details:Job Description: About the Role
Intel is seeking a Senior Design Verification Engineer for the Silicon Chassis team. In this role, you will own end-to-end verification of critical chassis and interconnect IP blocks from planning through signoff. You will drive quality in testbench architecture, test plan and coverage closure while working closely with architecture, design, and software teams. This position requires strong technical depth in DV methodologies, protocol verification, and memory subsystem behavior, with enough breadth in RTL, physical design, and CAD to contribute across traditional discipline boundaries. AI-assisted workflows are part of everyday development here. Consistent execution against schedule and quality goals is expected.
Responsibilities will include but are not limited to:
- Own verification planning and execution for key IP features across IP and subsystem integration points
- Build scalable verification environments and targeted test plans with reusable test benches, checkers, VIPs, and behavioral models
- Collaborate closely with architecture, design, and software teams from specification through bringup; contribute across role boundaries when needed to unblock progress and maintain execution quality
- Drive ownership of multiple critical blocks and verification components; take full responsibility for functional signoffs and achievement of performance and power metrics
- Lead IP delivery to multiple customers while ensuring technical excellence; balance competing requirements, schedules, and resources across teams
- Drive convergence of simulation and formal verification into unified bug hunting and coverage closure strategies; evaluate and adopt emerging methodologies including ML-driven verification flows
- Mentor and develop verification engineers; establish verification best practices and raise team-level execution quality
- Comfortable using AI-assisted development tools as part of everyday workflow; track record of delivering reusable, configurable verification collateral
Core Competencies
- Excellent communication and organizational skills with a track record of delivering high-quality silicon on schedule; able to adapt as tools, methodologies, and role definitions evolve
Qualifications:The Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
- Bachelor of Science Degree in Electrical or Computer Engineering, Computer Science, or in a STEM related field
- 10+ years of experience in design verification (DV); with extensive background in IP DV, and subsystem and SoC-level verification
- Experience in interconnects, caches, and memory subsystems, including multiple bus protocols such as AMBA (CHI, ACE, AXI), PCIe, UCIe, and CXL; cache coherency and memory consistency models
- Experience in verification of global functions including debug, trace, clock and power management, RAS, QoS, and security feature
- Experience in simulation and formal verification methodologies including UVM, SVA, ABV, and co-simulation; proficiency in low-power verification techniques, HDL/verification languages, and industry-standard EDA tools
- Hands-on coding experience across SystemVerilog/UVM, C/C++, Python, and build systems
- Experience working with RTL, physical design, and CAD tool flows; contribute outside core DV responsibilities as needed.
Preferred Experience
- Post graduate degree in Electrical or Computer Engineering, Computer Science, or in a STEM related field
- Experience with formal verification tools (JasperGold, VC Formal, or similar) and emulation or FPGA-based verification; track record of combining formal and simulation for unified bug closure
- Prior work with system IPs such as MMUs (SMMU or IOMMU) and interrupt controllers, and working knowledge of the associated software stacks
Job Type:Experienced Hire
Shift:Shift 1 (United States of America)
Primary Location: US, California, Santa Clara
Additional Locations:
Business group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $164,470.00-311,890.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
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