Senior Design Verification Engineer

Casa system   •  

Andover, MA

Industry: Telecommunications

  •  

8 - 10 years

Posted 164 days ago

This job is no longer available.

Job Description

Casa Systems, Inc. is a leading provider of next-generation broadband distributed and virtualized architectures in mobile, fixed telecom and cable networks. As the original supplier of commercially deployed CCAP systems that deliver voice, video, and data over a single port, Casa continues a tradition that brings leading edge solutions to hundreds of service providers around the world. At Casa Systems, our mission is to deliver ultra-broadband solutions that keep families, communities and the world connected. We harness our passion for innovation to drive technological solutions that allow service providers to do amazing things that improve the way we live.

 

We are seeking to hire a Senior Design Verification Engineer to join our Hardware Engineering team located in our Andover, MA, USA office about 30 minutes North of Boston.

 

The Senior Design Verification Engineer will be a member of the FPGA design verification team and will work closely with FPGA and design verification engineers to advance and improve the verification environment.

 

ESSENTIAL DUTIES & RESPONSIBILITIES:

 

  • Create and/or enhance test benches by developing a thorough understanding of the design under test.
  • Build reusable DV infrastructure components for module and top level environments.
  • Define and document test plans for module/block level (IP) and system level verification.
  • Identify and write coverage measures for stimulus and corner-cases.
  • Continuously improve the verification environment and methodologies, while ensuring the highest degree of quality by applying industry leading methodologies.
  • Define, implement, automate, and execute regression tests.

 

QUALIFICATIONS:

 

  • Undergraduate degree in Electrical Engineering, Computer Engineering, Computer Science or equivalent work experience required. Graduate degree preferred.
  • 7+ to 10 years of design verification experience with a proven track record of successfully verifying and delivering complex ASICs, FPGAs or SOC.
  • Working knowledge of functional verification including: test plan development, bus functional models, random stimulus generation, functional coverage, monitors, checkers, scoreboards, and sequencers.
  • Proficient in one of the following: UVM/OVM/VMM
  • Deep knowledge of Verilog and System Verilog.
  • Previous experience with one or more scripting languages such as Perl, Python, or TCL a plus.
  • Experience with industry standard protocols such as PCIe, DDR, DMA, and/or Packet Processing a plus.
  • Familiar with simulation environment using Xilinx and/or Altera FPGAs, a plus.
  • A passion learning new technology, solving complex problems, and delivering on quality.
  • Creative problem solving skills, attention to detail, and good coding skills are required.
  • Must be a self-starter capable of independently driving tasks to completion.
  • Must have good teamwork and interpersonal skills.

 

Tracking Code 695