The NVIDIA Clocks group is looking for a top ASIC engineer with proven experience in high-speed logic design and verification. In order to support high frequency clock domains, the complexity of clocking structure has increased significantly. Modern clocking design needs to balance high frequency clocks with power, DFT, noise, circuit and physical design constraints.
What you'll be doing:
- You'll design new clocks modules to support high frequency clock with all the above constraints.
- To deliver high quality clock modules, you'll verify clock design with the industry standard tools.
- Design novel techniques to distribute clocks over long distances with low insertion delay, skew and OCV effects.
- Additionally, you'll perform static timing analysis (STA) on the designed clock modules.
What we need to see:
- BS or MS (preferred) degree in EE with at least 3+ years of work experience
- Confirmed and shown knowledge with RTL design (Verilog), verification and synthesis
- Validated strong coding skills in Perl or other industry-standard scripting languages
- Strong communication skills, along with the ability to work in a dynamic product oriented team.
- Deep understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus