Date: May 8, 2018
Location:Milpitas, CA, US
Engineers in the Soc Architecture and Modeling Group have the rare opportunity to transform their creative ideas into best selling products. Candidate will be responsible for Architectural definition of the SSD Controller ASIC . The work would involve Modeling Systems, Algorithms , IP Explorations, and validating the Architectural implementation of Drive Subsystem to meet SSD product Spec. The candidate will be responsible for developing and delivering proof-of-concepts Models in C, C++ or other languages, based on various architectural explorations and flash translation layer Algorithms.
The Team’s Focus would be to Study Hardware and FirmwareAlgorithm and are responsible for defining ASIC features and Architecture to be used in future generation of products. The team members have the rare opportunity to get exposed to diverse space including Flash memory Technology, firmware, Engineering Development and product marketing. The candidate is expected to develop executable Software Models in some cases Hardware module and details architectural documentation of the system to be realized.
- ASIC Design Experience is required
- Knowledge of SSD system (Controller, Firmware) and related performance metrics, Nand Flash is Required .
- Knowledge of Next Generation Memories is desired
- Soc Architecture Experience is Required
- C, C++ / Java Knowledge required.
- Candidate should have Good communication verbal and written skills
- Proven ability to work as a team member both on the team and outside of the team.
- Must have zeal to learn new things and able to follow direction.
- Good understanding of Digital Logic Design, Storage Protocols, Storage Systems, Data Structures, Algorithm, Computer Architecture Theory
- Interest in Soc Development. Familiar with Verilog and Soc Design , FPGA design Flow is a plus
- The position typically requires Masters Computer Engineering or PhD Computer Engineering/Electrical Engineering.
- Minimum Experience : 5 years with Atleast 3 years in Soc Digital Design
- Position is not open to NCG
Keywords: SSD Architect , Soc Architect, SOC Architecture , SSD Architecture, ASIC Architect , HW Architect, NVME , Computer System , Performance Evaluation, Digital Logic Design
We recruit, hire, train, promote, discipline and provide other conditions of employment without regard to a person's race, color, religion, sex, age, national origin, disability, sexual orientation, gender identity and expression, pregnancy, veteran’s status, or other classifications protected under law. This includes providing reasonable accommodation for team members' disabilities or religious beliefs and practices. Each manager, supervisor and team member is responsible for carrying out this policy. The EEO Administrator in Human Resources is responsible for administration of this policy. The administrator will monitor compliance and is available to answer any questions on EEO matters.
Keywords: Milpitas || California (US-CA) || United States (US) || SSD Engineering || Experienced || Regular || Engineering || #LI-DG1 ||
Nearest Major Market: San Jose
Nearest Secondary Market: Palo Alto
Job Segment: Architecture, Engineer, Firmware, Electrical, Developer, Engineering, Technology