RTL Verification

  •  

Rockford, IL

Industry: Technology

  •  

8 - 10 years

Posted 165 days ago

  by    Cynet EngineeringTeam

Job Description:

  • Min 8year of exp

Overview:

  • DO254 FPGA V&V activities.
  • Experience in VHDL Coding & Design -Synthesis and Layout (includes timing closure and constraints generation)
  • Experience in creating of VHDL Test-benches
  • Experience in performing VHDL test-bench Verification ? Cadence NC-VHDL
  • Code Coverage Analysis - TransEDA
  • Independent Simulator Verification of RTL simulation - ModelSim
  • Should be able to perform Corner (Min, Max, Typical) Post Layout Simulation (using back annotated netlist and .sdf data)
  • Creation of Verification Traceability Matrix against MRD requirements
  • It would be nice to have experience in DOORs & exposure to UTAS standard Works

Primary Skills:

  • Experience in VHDL Coding & Design -Synthesis and Layout (includes timing closure and constraints generation)
  • Experience in creating of VHDL Test-benches 
  • Experience in performing VHDL test-bench Verification ? Cadence NC-VHDL
  • Code Coverage Analysis - TransEDA
  • Independent Simulator Verification of RTL simulation - ModelSim
  • Should be able to perform Corner (Min, Max, Typical) Post Layout Simulation (using back annotated netlist and .sdf data)
  • Creation of Verification Traceability Matrix against MRD requirements
  • It would be nice to have experience in DOORs & exposure to UTAS standard Works

Education:

  • B.Tech/B.E

NOTE:

  • Effective communication skills