RTL Design Engineer in Mountain View, CA

$100K - $150K(Ladders Estimates)

Synopsys Inc   •  

Mountain View, CA 94035

Industry: Information Technology

  •  

5 - 7 years

Posted 54 days ago

Job Description and Requirements

Participate in the development of DDRPHY IP Architecture and Microarchitecture specifications for the IP


  • Verilog RTL development and debug, publish and maintain design spec and micro-architecture spec
  • Work closely with architect in design definition and implementation
  • Work closely with verification team for test plan/strategy to meet all functional requirements and performance
  • Work closely with Verification team in defining verification strategy and reviewing test plan.
  • Work closely with timing and physical team for timing closure and meet power and area goals
  • Qualifications
  • BS/MS in Electronics Engineering with minimum of 5 years of ASIC frontend & behavioral modeling experiences
  • Strong in communication, leadership, investigation, problem solving & analytical skill
  • Proficiency with Verilog RTL coding (LEC, CDC, DFT)
  • Well verse in interface timing budget & clock domain crossing design
  • Knowledge of VCS, Co-sim, Conformal LEC is an advantage.
  • Familiar with SoC designs and micro-Architecture
  • Knowledge of DDR memory and DDRPHY architecture is a plus


Valid Through: 2019-10-18