THE ROLE

AMD is seeking a Silicon Design Lead to join a high019performing team responsible for the design and development of complex silicon IP. This is an RTL design role focused on digital design for memory/PHY (DDR/PHY) subsystems, working across architecture, verification, and physical design to deliver high019performance solutions.

THE PERSON

You are a highly experienced RTL design engineer with strong technical judgment and the ability to lead workstreams across a small team. You communicate clearly, collaborate effectively across organizations, and take ownership of complex design challenges.

You are comfortable providing technical leadership of a small team and driving execution, with the expectation that this role focuses on managing work.

KEY RESPONSIBILITIES

• Own microarchitectural design and RTL implementation of major IP features and sub-systems
• Drive PHY digital architecture development from pathfinding and high-level architecture to RTL coding, verification, and support for physical implementation
• Interpret and apply JEDEC DDR/LPDDR specifications to ensure standards-compliant PHY and controller behavior
• Collaborate closely with the Firmware team to define, implement, and optimize firmware sequences and algorithms
• Synthesis, STA, CDC/RDC, UPF Design/Simulation, Power optimization, Gate sim
• Analyze RTL design for power, performance, and area (PPA); guide optimization strategies and tradeoffs
• Partner with Design Verification teams to define verification strategies and ensure robust coverage of design features (including UVM-based environments)
• Drive timing synthesis, constraints definition, and support backend teams through physical implementation and signoff
• Lead and participate in design specification reviews, microarchitecture reviews, and RTL code reviews; enforce high-quality design practices
• Introduce, evaluate, and deploy new EDA tools, scripts, and methodologies into the workflow to improve productivity and quality
• Provide technical leadership, mentorship, and day-to-day guidance to junior and intermediate engineers
• Collaborate with cross-functional teams (architecture, analog/mixed-signal, PD, FW, verification) to resolve complex integration issues

PREFERRED EXPERIENCE

• Solid industry experience in digital design engineering, with a focus on complex SoC/IP blocks.
• Strong experience with DDR / LPDDR PHY and/or Memory Controller design,
• Good working knowledge of JEDEC DDR/LPDDR specifications
• Experience translating spec requirements into microarchitecture and RTL
• Excellent knowledge of Verilog and SystemVerilog for design; C/C++ experience is a strong plus
• Proficient with scripting for automation and flow development; experience withPythonis preferred
• Demonstrated ability to bring up anddeploy new EDA toolsand methodologies into an existing design flow (e.g., lint/CDC/Formal, power analysis, synthesis, static timing, coverage, regression infrastructure)
• Proficient in debugging firmware and RTL code using simulation and waveform tools
• Experience working with UVM testbenches and verification environments
• Comfortable working in Linux-based development environments; familiarity with Windows is a plus.
• Knowledge of clocking architectures, synchronization techniques, and CDC (Clock Domain Crossing) methodology
• Strong understanding of computer organization and microarchitecture
• Mixed-signal RTL experience (e.g., interfaces to analog front-ends, calibration/control logic) is a plus
• Leading small design teams or technical sub-projects
• Providing mentorship, code reviews, and technical guidance to junior engineers
• Influencing architectural and methodology decisions

ACADEMIC CREDENTIALS

• Bachelor019s or Master019s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (preferred)

LOCATION: Vancouver, BC

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Benefits offered are described: AMD benefits at a glance.