RTL Design Engineer

Salary depends on experience
Posted on 09/21/17
Santa Clara, CA
Business Services
Salary depends on experience
Posted on 09/21/17

RTL Design Engineer

  • Job Number: 112979996
  • Santa Clara Valley, California, United States
  • Posted: 30-Aug-2017
  • Weekly Hours: 40.00

Job Summary

You will join the DDR PHY design team. We provide best-in-class PHY designs for high-performance, low power applications. As a logic design engineer, you will be involved in all phases of the design, from concept study, architecture definition, design and verification, to silicon bring-up and characterization.

Key Qualifications

  • The ideal candidate will have five or more years of experience in logic design with the following qualifications:
  • RTL design using Verilog or SystemVerilog, assertion writing
  • Design of state machines, data paths, arbitration and clock domain crossing logic
  • Logic synthesis, timing constraints
  • Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL
  • Unified Power Format for simulation, synthesis and electrical rule checking
  • Equivalence checking
  • Prior experience in DDR PHY design and mixed-signal environment is a plus


In this role, you will be responsible for: Performing concept studies and provide guidance in terms of performance, gate count and power for various digital designs. Writing detailed design specification and test plans in close cooperation with architecture, circuit designers and verification engineers. Providing high-quality RTL description, including assertions, for the design. Formal tools and static checkers will be used to guarantee RTL quality. Supporting design verification to insure bug-free first silicon. Driving functional and code coverage as well as timing closure for your designs. Supporting silicon bring-up, performance and power characterization.


B.S. / M.S. in Electrical Engineering or Computer Science required.

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