At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. RTL and Architecture Design Director (DDR)
This is an opportunity to lead and innovate in the design of next-generation Memory subsystem Design IPs at Cadence. These advanced technology node IPs will enable the futuristic SoCs for Datacenter, Edge computing, Automotive and AI applications.
You would also be leading a team of experienced and new engineers and direct microarchitecture efforts across multiple memory interface PHY product families. These span futuristic clocking architecture, Datapath and training logic micro-architecture and RTL design decisions targeted at better timing, PPA, based on pre and post implementation timing analysis.
You will also have responsibilities as front-end design leader of a PHY Design team, responsible for development of productization of one of the PHY architectures. Your team's responsibilities will span across various aspects for the ASIC frontend flow, which includes developing micro-architecture/design specifications, implementing RTL code for complex digital logics, RTL integration, synthesizing and optimizing the design for better timing, PPA, doing performance analysis, setting up block level test bench, collaborating with the verification team and analyzing the coverage results. Required Experience & Qualifications
- BSEE/MSEE and overall 15 years of prior industry experience required
- 5+ years' experience as a team manager directing efforts of RTL team on various frontend activities
- 5 + years' Experience as a PHY architect or micro architect that resulted in successful IP or products
- Strong design experience in RTL and timing issues prevalent in design of high-speed interfaces.
- Deep knowledge of best practices and flows in RTL design and ASIC methodology - physical synthesis, linting, early power estimation, UPF flow, Design for test, STA and equivalence checking.
- Ability to handle multiple projects/tasks successfully
- Experience in working with Analog, SI, package engineers and possess a system view of high speed interfaces and their applications
- Team player with a passion to innovate and can-do attitude.
- Self-starter and highly motivated
- Knowledge of DDR/GDDR DRAM protocols and memory subsystems
We're doing work that matters. Help us solve what others can't.
- Experience in high speed and low power digital design using advanced deep micron process.
- Experience with highly configurable designs
- Experience designing or integrating IP