R & D Scribe Design Engineer

5 - 7 years experience  •  Business Services

Salary depends on experience
Posted on 11/22/17
5 - 7 years experience
Business Services
Salary depends on experience
Posted on 11/22/17

As a Scribe Design Engineer in Micron’s R&D Scribe Design group, you will support advanced technology development through scribe test structure design and layout, scribe database management and reticle creation.  The candidate will progress to take responsibility for a part types test structure development and requires the initiative and communication skills to drive a project through multiple phases to completion. Job functions include: Test structure design and layout, Interaction with Process Integration teams, reticle tapeout, assisting in Keithley/Agilent param program development and assisting with param correlation and debug.  Exciting opportunities exist to participate in the development of new emerging R&D technologies.  

 

You will support process development activities through close interaction with Process Integration, Advanced mask development/OPC team, Product and Design engineering, R&D and production Fab engineers, Maskshop Development engineering, as well as characterization engineers to create standardized and novel test structures.  This includes feedback between these groups during the initial development of an R&D project on through Manufacturing integration. You will also be expected to create and maintain test structure documentation and related parametric information.

 

Additionally you will support process development activities through close interaction with Process Integration, Advanced mask development/OPC team, Product and Design engineering, R&D and production Fab engineers, Maskshop Development engineering, as well as characterization engineers to create standardized line test structures. Training will be available in process development, simulation, layout environments and utility programs, also mentoring in test structure design, verification and best practices.

 

 Responsibilities:

Responsibilities for this position include, but are not limited to, the following:

  • Test structure definition and customer interaction.
  • Layout of test structures.
  • Documentation and related parametric information.
  • Quality metrics for the structures.
  • Joint development of CAD tools and methodologies for automating and/or increasing productivity of physical layout design using programming languages such as: Perl, SKILL (Cadence), and unix shell scriptinglanguages. The Scribe CAD team will be a partner in this development.
  • Create and maintain test structure documentation and related parametric information.

 

 Qualifications:

The successful candidate for this position will have a selection of skills from the list below:

  • Good understanding of state-of-the art CMOS device physics and electrical design.
  • Process integration experience on CMOS technologies.
  • An understanding of electrical device characterization, and the relation of test structure layout to measurement results
  • Layout and Verification skills in Cadence and Calibre.
  • Knowledge of memory technologies and design is a plus
  • A strong work ethic that is driven to succeed,
  • Strong troubleshooting and problem solving skills
  • The ability to multi-task with good organizational skills
  • Excellent communication skills, both oral and written.

 

 Experience and Education:

 MS in EE, Physics, or related discipline or BS + 5 years of experience.  Preferred candidates should also have >2 years of experience in layout, Process Integration or close interaction with scribe structures as a customer.

 

We recruit, hire, train, promote, discipline and provide other conditions of employment without regard to a person's race, color, religion, sex, age, national origin, disability, sexual orientation, gender identity and expression, pregnancy, veteran’s status, or other classifications protected under law.  This includes providing reasonable accommodation for team members' disabilities or religious beliefs and practices.

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