Job Description and Requirements
Synopsys is hiring a Senior R&D Engineer for our Logic Library Group in Mountain View, CA. The ideal candidate will have extensive experience in the following areas:
- 6+ years of experience with semiconductor process bring up for advanced nodes
- Cell library architecture co-optimization with process
- Developing cell design guidelines to optimize PPA and DFM at cell level and design level
- Optimizing FEOL and BEOL elements to support cell optimization
- Cell library and process co-optimization with EDA tools and flows
- SoC design flow bring-up: Develop synthesis, P&R, and verification flows, identifying gaps in tool capabilities and developing enhancement specs for tools
- Making a case for tool enhancements by developing prototyping scripts/flows to demonstrate their benefit
- Tuning BEOL elements to optimize power distribution, EM robustness, and RC delays
- Prediction of SoC level PPA from the above activities
- Ability to work effectively with geographically distributed R&D teams, and to engage in cross-functional collaborations for optimization across the entire design chain.
- Effectively articulate ideas and requests to drive such collaborations.
- Ability and willingness to do hands-on development as well as mentoring and coaching junior R&D engineers to expand their skills.