Job Description and Requirements
Synopsys is hiring an R&D Engineer to work on Standard cell Layout design for the Logic Libraries. You will be working on advanced FINFET based process nodes for standard cell layout design , while fostering a productive and collaborative work environment with the teams across the world.
Your responsibilities include:
- Designing and laying out standard cell circuits; closely working with circuit designers, Layout architect and Physical design engineers to achieve the best in class Standard cell libraries which are optimized for performance, area and power.
- Understanding physical design rule documentations
- Working on layout design of multiple foundries
- 8+ years of industry experience in Layout design, with preference given to those with Standard cell design in finfet nodes
- Experience in scripting languages such as Perl, Python, Tcl etc.
- Experience in Electro migration, IR drop, Reliability would be an advantage.
- Exposure to working in global design team environment with different cultures
- Strong problem-solving skills, self-driven and excel in creating highly differentiated best in class Standard cell solutions for complex designs in the market.
- Continuous improvement in technology, meeting organizational goals and logic libraries development.