As a member of our Broadcom Mobile and Wireless organization, you will be part of a physical design team implementing the latest advances in Bluetooth, and the broadest line of Wi-Fi® integrated circuits in the industry.
You will be responsible for 28nm/16nm/7nm block and chip level physical design, developing and executing synthesis, formal verification, static timing analysis, low power verification, lint and CDC flows.
Primary focus will be on developing and maintaining the timing constraints for block and SoC level, running STA and generating timing ECO's.
Positions available at Principal Engineer level. Title will vary based upon candidate's experience and abilities, with a BS/MS/PhD degree + 10 years of experience as the minimum required.
- Experience in writing and verifying timing constraints for synthesis and static timing analysis is required
- Familiar with Timing-Sign-Off of complex SOCs in deep sub micron CMOS technologies using state-of-the-art EDA tools (PrimeTime, Cadence ETS / Tempus, GoldTime), with advanced margin models (AOCV, POCV, SOCV).
- Knowledge of deep sub-micron technology and trade-off between power, speed and area
- Experience with Logic Vision Memory (MBIST) and Logic Bist (LBIST) is plus
- Should be very comfortable writing scripts in TCL and Perl to achieve higher performance and productivity through automation
- Must be well organized, methodical, and detail oriented
- Must have excellent interpersonal and communication skills