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Job Description Summary
DDR IP Principal Design Engineering Position Description:
This is a unique opportunity to join the rapidly growing the DDR IP R&D Group at Cadence Design Systems. We are looking for a Principal Design Engineer who will be the main technical interface on Key Customer engagements deploying our advanced high speed DDR/GDDR solutions.
o Primary interface between Cadence DDR IP R&D and customer engineering teams integrating latest advanced DDR interconnect IP.
o Responsible for integration / customization / verification of IP subsystems using Cadence's latest advanced DDR PHY and controller IP technology.
o Analyze and resolve complex subsystem application or implementation issues and provide professional guidance to customers.
o Support customers using new DDR product with silicon bring up and lab testing.
o Work very closely with R&D silicon validation team to ensure successful customer silicon bring up success, for latest DDR interface IP.
o Support PHY and controller SOC integration reviews, and integration questions.
o Perform RTL and gate level simulations to verify functionality.
o Develop and optimize comprehensive test automation
o Generate technical DDR specifications, data sheets, and application notes.
o Update R&D team with the latest customer feedback and competitive analysis.
o M.S. Electrical/Computer Engineering (or similar degree)
o 7+ years' experience
o Experience working with or developing DDR Interface IP.
o Verilog RTL design and gate level verification experience.
o Strong debug and problem-solving skills.
o Experience in SOC design implementation, from RTL to final GDS and final production ramp.
o Hands on experience with SOC digital design methodology and tools.
o Synthesis and STA experience, back-end experience is a plus
o Familiarity with industry standard DFT flows and test methodologies.
o Experience with embedded firmware development
o Verilog, Tcl, C, Perl, Python
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Valid through: 11/19/2021