At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Principal Design Engineer – Tensilica IP Backend Physical Design
Searching for an intelligent, inventive, self-starting engineer interested in developing new backend flow methodologies with the Cadence EDA toolset. You will be joining a small team of capable individuals with significant visibility throughout the entire Tensilica IP group within Cadence. You have a strong understanding of all stages of placement, CTS, routing, extraction and timing signoff, with a goal of optimizing power/performance/area of complex multi-processor Tensilica subsystems. Experience with the latest process technologies and concepts (CNOD leakage, via pillars, layer promotion, etc.) a plus.
- Develop and maintain the Innovus-based place-and-route flow for our Tensilica processor IP product line, including floor-/power-planning of large (>40M gate) multicore solutions
- Collaborate with the RTL design team to determine PPA tradeoffs for different processor architecture options
- Participate in occasional benchmarking exercises for customer engagements
- MSEE / MSCS and at least 5 years of experience with EDA flow development and usage
- Strong understanding of digital logic design and computer architecture
- An inquisitive, inventive mind
- Excellent verbal and written communication skills
High value additional skills:
- Knowledge of Perl, Make, and TCL scripting
- Experience with low power techniques (PSO) using UPF or CPF
- Experience with the Cadence digital EDA toolset (Genus / Innovus / Quantus / Tempus / Conformal) in the latest FinFET technologies
We’re doing work that matters. Help us solve what others can’t.