Principal Verification Engineer
The group requires a ASIC verification engineer with extensive experience on networking ASIC verification, with in-depth knowledge of verification methodology and tools, good problem solver, excellent communication, as well as proven record of delivering functioning silicon.
You will be part of a verification team responsible of delivering ASICs for complex networking systems. You will collaborate with architects, design team, hardware and software teams within the company during the project.
Participate in functional and micro-architectural discussions with design team
Develop verification plan for module and/or chip-level verification based on design specs.Conduct initial test plan review, test object review, and exit reviews.
Develop testbench as well as tests, including models, drivers, monitors, and checkers
Gather and improve code coverage and functional coverage with designer’s feedback
Provide mentoring and guidance for other team members in verification methodology and tool usage.
Minimum 10years of ASIC verification experience
Fluent in SystemVerilog and UVM programming, and ability to leverage and reuse verification components from module level
Strong problem solving and debugging skills
Excellent written and verbal communications skills
Knowledge of high performance memory subsystems
BSEE is required
12 or more years of ASIC verification experience is preferred
Experience with networking protocols (Ethernet, IPv4/v6, or MPLS) is a plus
MSEE or above is preferred