As a Principal Advanced DRAM Engineer, you will be responsible for the design and development of next generation DRAM products. You will work in an integrated structure combining both Product and Design engineering subject areas. The team will execute a common goal of ensuring our future roadmap is successful.
You will apply a deep understanding of array parasitic, speed/timing bottlenecks, sense amp margin, CMOS gate variability, and characteristics to drive design optimization and innovations that target the best in class die size, quality, reliability, and power.
Responsibilities and Tasks include the following, but not limited to:
- Assist with the overall design, layout, and optimization of memory circuits
- Perform circuit simulations using standard industry tools such as SPICE and VERILOG
- Assist in the design and development of schematic blocks such as memory array, control logic, address decode, datapath, and internal test logic.
- Understand the impact of design architecture decisions on overall power, speed, and die size
- Optimize design rules for cost, performance, and functionality
- Import layout parasitic information into the circuit simulation environment
- Able to interpret device specifications to produce the required functionality.
- Build solutions and define requirements for circuit operation, DFM is a key focus.
- Develop strategies to support development through test chip definition and silicon validation
- Look for opportunities to drive competitive advantages into our solutions by developing groundbreaking ideas and concepts.
- Responsible for reliability verification.
Qualifications and Skills include, but not limited to:
- 10+ years of Product or Design Engineering experience.
- BSEE or greater
- Analog circuit design and/or debugging experience.
- Simulation experience
- Strong understanding of array core architectures, circuits, & functions.
- Strong communication skills with the ability to convey sophisticated technical concepts to peers and management.
- uMATE & wafer bench data gathering experience a plus
- Good DFT/DFM understanding with the knowledge of PROBE and Backend test flows a plus
- Experience with shell scripts and data extraction of production data a plus
- Experience and understanding MFG process flows / Layout / Defect analysis a plus
- Experience with Automated Test Equipment (C1D, Advantest, AMBYX…) a plus