Physical Design Verification Engineer

Salary depends on experience
Posted on 09/22/17
Business Services
Salary depends on experience
Posted on 09/22/17

Physical Design Verification Engineer

  • Job Number: 32821198
  • Santa Clara Valley, California, United States
  • Posted: 01-Sep-2017
  • Weekly Hours: 40.00

Job Summary

In this highly visible role, you will be responsible for physical verification of an SOC.

Key Qualifications

  • The ideal candidate will have 5-10 years of physical design experience, with emphasis on physical verification.
  • Strong knowledge of physical verification flows and methodology.
  • Knowledge of all aspects of ASIC physical design.
  • Scripting skills to debug flow related issues and make enhancements as appropriate.
  • Experienced in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc.
  • Real chip tapeout experience with a track record of successful signoff.
  • Layout design background and experience a plus.


As a member of the physical design team, you would be responsible for: - Performing various types of physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield, and lithography) at the chip and block level • Interfacing with the CAD/Technology teams for flow bring up and validation • Working with the Implementation team during the entire chip design cycle to drive signoff closure for tapeout • Managing schedules and supporting cross-functional engineering effort - Work on padring, bump, RDL design interfacing with the package and floorplan teams



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