Master’s Degree in ElectricalEngineering with 10+ years of Industry experience
Physical synthesis with placement/routing studies for design optimization & convergence.
Complete floorplan including power domain planning, clocks and complete any simulations needed to prove out line of sight to design convergence.
Experience with FinFet nodes (16nm, 14nm, 10nm) and Proven experience in achieving timing coverage at 2Ghz+ Frequencies
Ability to independently own all aspects of block level implementations of large blocks ~3-5M gates.
Investigations and full-chip critical path analysis.
Synthesis run with initial UPF on latest RTL to get top-level connectivity analysis
Expertise with Synopsys tool suite (ICC2) is must.