Physical Design/Implementation Engineer, ASIC

Google   •  

Mountain View, CA

Industry: Technology


Less than 5 years

Posted 170 days ago

This job is no longer available.

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

You will be part of Google’s Consumer Hardware team, developing high performance and low power hardware to enable Google’s continuous innovations in mobileworking with Application Specific Integrated Circuits (ASIC).

You will work with Architects and Logic Designers to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs for physical design closure. You'll also work with Verification and Software teams to understand and implement the design requirements for clocking and power management.

Google's mission is to organize the world's information and make it universally accessible and useful. Our Hardware team researches, designs, and develops new technologies and hardware to make our user's interaction with computing faster, more powerful, and seamless. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, our Hardware team is making people's lives better through technology.


  • Develop all aspects of Application Specific Integrated Circuit (ASIC) implementation with emphasis on physical synthesis, place and route, static timing analysis, design for testability Verilog generator, third-party IP integration and DVFS in advanced technology nodes.
  • Manage block and full-chip level physical implementation and QoR (power, timing, area).



  • BS degree in Electrical Engineering or related field or equivalent practical experience.
  • Experience in one or more of the following areas: ASIC physical design, digital design and/or physical design flows (synthesis, place and route, STA, DFT, formal verification, CDC, and power analysis, power intent (UPF/CPF), IR/EM analysis).
  • Experience working with one or more of the following tools: Design Compiler, ICC/ICC2, Innovus/EDI, Primetime, Conformal, Spyglass and/or Power Artist.


  • 1 year of experience in ASIC physical design flows and methodologies in 7nm-40nm process nodes.
  • Experience and/or knowledge of high level synthesis (HLS).
  • Experience in IP integration (memories, FLASH, IO’s and Analog IP).
  • Experience in extraction of design parameters, QoR metrics and analyzing trends.
  • Knowledge of semiconductor device physics, transistor characteristics and multiple foundry.
  • Knowledge of Verilog/SystemVerilog scripting and effective scripting skills with Python, Tcl, and/or Perl.