As part of the physical design team, own and implement large partitions of high-performance processor blocks using digital design implementation tools.
What you'll do
- Design, and implement solutions using knowledge of timing, floor-planning, high speed design techniques, and formal verification techniques.
- Apply semi-custom, and ASIC-methodologies, as required, to run, synthesis, placement, CTS, routing, and complete other physical design tasks to make the block ready for sign-off.
- Use EDA tool-based programming and scripting techniques to automate and improve throughput and quality.
- Implement lower-geometry designs using CMOS-7nm rules, device characteristics to implement data-paths, and large physical blocks.
- Use state-of-the-art macro-compilers, design-cell libraries to provide appropriate design libraries to the processor design team.
What you'll bring
- Hands on experience in floor planning, place & route, power and clock distribution, pin placement and timing constraints generation
- Timing convergence using high speed design techniques
- Physical design of high frequency chips with emphasis on successful timing closure
- Excellent understanding of geometry/ process/ device technology implications on physical design. 16nm and 7nm experience is required
- Good understanding of static timing analysis (STA), EM/IR and sign-off flow
- Experience in physical design verification
- Good programming/scripting skills: Tcl, python, expect, shell
- BS/MS and 8+ years; Master’s Degree (MS): Electrical Engineering, Specialization: VLSI design, high-speed microprocessor design
Perks in Santa Clara
- Office has panoramic views of Silicon Valley
- Garage parking, including charging stations and bike parking
- Gym and café on campus
- Healthy snacks, espresso, and drinks
- Standing desks
- Game room, including ping-pong
- Unlimited Flextime and 10+ paid holidays