Physical Design Engineer 2 at Advanced Micro Devices, Inc in Santa Clara, CA

What you do at AMD changes everything

At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center.

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

The Role:

We are looking for an innovator and hardworking Engineer to join our team! Someone that can work in a fast pace environment and able to thrive on new challenges.

We have competitive benefit packages and award-wining culture. Join us!

The Person:

The person for this role would need good communication skills & analytical thinking skills to be successful. Also, should have the ability and desire to foster a team environment.

Key Responsibilities:

• Responsible for leading the pre-silicon SOC level design.
• Responsible for Front-End chip implementation including design integration, synthesis and execution flows that starts with RTL coding and ends with the delivery of a netlist package ready for physical design.
• Responsible for synthesis, netlist generation, timing and logical equivalency checks, floorplanning, budgeting, clock methodology and timing constraint management.
• Work in collaboration with Physical Design Engineers in chip level planning and integrations.

Preferred Experience:

• Experience in complex ASIC Design.
• Direct experience in SOC or Graphics/Video is plus.
• Have in depth knowledge of entire design process from Design specification, defining architecture, micro-architecture, RTL design and functional verification, synthesis, Physical Design, Timing closure, Tape-out, and post-Si debug.
• Have hands-on experience in Chiplevel Design/Integration activities.
• Some Physical Design exposure required.
• Lead a team and provide Technical mentoring and guidance to junior engineers.
• Perform Synthesis and net listing tasks such as SDC Development, Scan Insertion, ECO implementation, Formal Verification, etc.
• Some exposure to DFT is a strong plus.
• Work with Physical Design team on Floor Plan, budgeting, timing closure, Signal Integrity, ECO flows, Power analysis, IO PAD placement, etc.
• Should have expertise in: Cadence RTL Compiler, Design Compiler, PrimeTime, Conformal LEC. Good knowledge of datapath compilers is required.
• Should have proficiency in flow development and scripting.
• Expertise in Perl and Tcl is a must.
• Should be able to work closely with RTL Designers and Backend Physical Design teams across multiple sites
• Knowledge of chip bus interfaces such as AHB and various standard peripherals & interfaces is a plus.
• Should be able to work closely with RTL Designers and Backend Physical Design teams across multiple sites

Academic Credentials:

Masters in CS/EE with relevant course work and project background with 2+ years of experience, or Bachelor’s with 3+ years of experience