Terms: Contract with Possible Extension
Successful candidate would be involved in the development of wearable's (watches, bracelets, pendants, etc.) with specific responsibilities including the layout of rigid and flexible PCBs
. As a PCB Design Engineer, you will be collaborating withother engineers and design teams to choose board technologies, determine board stack-ups, and iterate on component placements and routing studies.
You will help achieve the right balance between cost, size, and manufacturability on a project-by-project basis. The candidate will maintain technical coordination with cross functional groups including EEs, MEs, Test, EMC, etc. You will resolve PCB design issues with fabrication and manufacturing vendors.
We are looking for a self-starter and a team player who can thrive in a dynamic startup-like environment. Someone with a lot of passion to contribute to the design and has the ability to come up with some innovative solutions to problems. Strong communications and organizational skill and the ability to multitask across various disciplines and tasks are a must.
Required Skills and Experience, not limited to the following:
- Proficient with the Cadence Design Entry CIS, Allegro and Cadence Constraint Manager (v16.6 or later)
- Flexible PCB Design experience is needed for this role
- 5+ years of related consumer product PCB layout experience utilizing Cadence Allegro and possess deep knowledge of layout-related signal integrity fundamentals.
- 1 or more years of experience with creating PCB layout symbols and logic symbols using Cadence tools.
- Must possess knowledge of high volume manufacturing technologies and production variance for rigid, rigid-flex, and full flex PCBs. CW will be a part of the New Devices Group working on wearable devices. The team consists of 2 Designers, 1 Component Engineer, and 1 contractor. The group is fast paced with a start-up feel and compressed schedules. We support about 4 engineering teams within NDG.
- Cadence Allegro and possess deep knowledge of layout-related signal integrity fundamentals
- Examples include, but not limited to, differential pair routing, power plane management, HDI, bypassing capacitor placement strategies, ground via return paths and shielding, RF design etiquette, clock signal routing, mixed signal design, any layer vias, balanced stack-ups, etc.
- Examples may include ability to search and navigate CIS database within OrCAD, general understanding of netlisting errors and fixes, how to apply net properties like diff pairs or buses, etc.
- Knowledge of Allegro Constraint Manager to set up diff pair spacing rules, length matching, x-nets, constraint regions, class to class rules, net shorts, etc.
- Examples may include mapping step models to PCB footprints and making adjustments to component step model
- SKILL and/or TCL/TK programming experiencerequired
Minimum Education: AS degree with emphasis in Engineering. CID/CID+ certification a plus
Knowledge of ProE/Creo and STEP files a plus