We are looking for Parallel Programming Application Developer for FPGAs for our client in Hudson, MA
Job Title: Parallel Programming Application Developer for FPGAs
Job Location: Hudson, MA
Job Type: Contract 12 Months
"US citizens and those authorized to work in the US are encouraged to apply. We are unable to sponsor H1b candidates at this time."
- The candidate will develop parallel applications on Altera FPGA, benchmark and identify potential bottlenecks between the host application and the device kernel(s) or in the kernels.
- The candidate will implement application prototypes and advanced concepts in OpenCL as well as parallelize OpenCL applications using the concept of pipelining to use several FPGAs.
The candidate will:
- Develop and implement prototype OpenCL programs and advanced concepts working with or under the guidance of architects.
- Implement and parallelize OpenCL applications to use several FPGAs using the concept of pipelining.
- Enable an existing Deep Learning framework such as Tensorflow to take advantage of parallel concepts.
- Perform benchmarking of applications as well as debug potential performance bottlenecks and optimize applications as needed.
- Preferred – Masters Degree or higher in Computer/Electrician Engineering
- Bachelor's degree with at least 5-7 solid years in the skills needed
- PhD – new college grad with experience in the skills needed.
- #1 Proficient at developing parallel applications or algorithms (e.g. ScalaPack etc.) with MPI and OpenMP from "scratch" or the beginning. Must know how it works and how to problem solve, debug and fix any issues
- #2 In-depth familiarity with AI and DL (Deep Learning)
- #3 Experience with Tensorflow including as a user, developer, etc. Good understanding of Training and Inference algorithms as well of communication patterns in the various graph e.g. Alexnet, ResNet50.
- Experience in all aspects of developing OpenCL programs for FPGAs (e.g. debugging, profiling, performance optimization, etc.) - If candidate has MPI and OpenMP then OpenCL can be trained
- In-depth familiarity with Altera FPGAs and toolset. – Nice to have
- C/C++ is desired
- Team working skills
- Good communication and interpersonal skills
- Hands-on candidate needed
- The work day starts between 8 and 9am. No exceptions
- Sponsor is working on funding for an additional 12 months for this position.