Located in Folsom California, at the base of the Sierra Nevada Mountains, Micron is one of the world's largest memory company. We are currently looking to hire for a senior level engineering position into our NAND Product Engineering Group.
This individual contributor role will be responsible for providing technical guidance to a team of engineers that will test (Pre Silicon and Post Silicon), validate and deliver leading-edge flash memory products. Role also involves determining test strategies and methodologies for future products. The products are primarily 3D NAND memories.
The job responsibilities would include:
- Post Silicon: Guide a team of engineers to resolve and debug issues through the entire test flow – front end to backend. Leading Task forces as appropriate to resolve issues.
- Pre Silicon:
- Determine right test methodologies, DFT and flows for cutting edge 3D NAND products.
- Aid probe and test teams with test mode simulations, validation and verification
- Propose new DFTs to fit the changing landscape of memory testing.
- Improve and innovate in test methodologies and test flows to improve product yield, quality and time to market.
- Work with Principal engineers in other areas to ensure robust end to end product test coverage.
- Communicate ideas clearly and develop effective technical strategies for the success of the product.
- Cross site and worldwide collaboration will be an expectation.
- Developing/Training the team through training forums and knowledge proliferation.
Additional responsibilities include proposing circuit design fixes, yield improvement, data analysis, failure analysis, qualification, and establishment of manufacturability prior to product ramp.
Position requires extensive interface and partnership with Test Engineering, Process Engineering, Design, Reliability, and Manufacturing groups.
Ability to do hands on technical work and 5+ years of technical leadership experience.
Expertise in test methodologies for NAND products, design simulations and identifying/fixing design bugs and Verilog.
Familiarity with ATEs and their usage, C++, Python, Statistics and Failure analysis.
Knowledge of semiconductor device physics is required. Must be self-motivated, have good written and verbal communication skills, work well in a collaborative team environment that spans multiple company sites.