Req. ID: 118422
The Design Engineer in the Non-Volatile Memory Group at Micron Technology, Inc., will be a technical individual contributor in design and validation of the on-chip controller and mixed signal circuitry in NAND FLASH chips. In this highly visible and challenging role, your responsibilities will include architecture development and product definition, system integration and full-chip and block-level validation plan and execution. Also RTL design and implementation of the controller hardware, synthesis, APR and full timing closure as well as development of firmware code for NAND internal operations. You will be working very closely with design teams both domestic and overseas on different projects
· Knowledge and/or experience in large scale design projects is desirable.
· Knowledge of Digital ASIC Design methodology is required.
· Solid knowledge and experience in Verilog language.
· Knowledge and/or experience in synthesis and static timing analysis is desirable.
· Knowledge and/or experience in non-volatile memory design (NAND in particular) is a strong plus.
· Experience with mixed-mode design and validation is a plus.
· Hands-on experience with Design/Verification CAD tools such as NCSim, Design Compiler, Formality, PrimeTime, etc.
· Knowledge and Experience with transistor level simulators such as Spice, Ultrasim, HSIM is desirable.
· Knowledge of SystemVerilog, UVM is a plus.
· Knowledge of TCL, PERL or Python is a plus.
· Ability to establish and maintain good relationships with colleagues
· Self-motivated, self-directed, and a team player (on the same team and outside of the team).
· MS degree or BS + 5 years’ experience required.
We recruit, hire, train, promote, discipline and provide other conditions of employment without regard to a person's race, color, religion, sex, age, national origin, disability, sexual orientation, gender identity and expression, pregnancy, veteran’s status, or other classifications protected under law. This includes providing reasonable accommodation for team members' disabilities or religious beliefs and practices.
Each manager, supervisor and team member is responsible for carrying out this policy. The EEO Administrator in Human Resources is responsible for administration of this policy. The administrator will monitor compliance and is available to answer any questions on EEO matters.
Keywords: Folsom || California (US-CA) || United States (US) || NVE (Non-Volatile Engineering Group) || Experienced || Regular || Engineering || #LI-RS1 ||
Nearest Major Market: Sacramento
Job Segment: Engineer, CAD, Firmware, Drafting, Design Engineer, Engineering, Technology