MTS Functional Verification Engineer

Advanced Micro Devices   •  

Boxborough, MA

8 - 10 years

Posted 175 days ago

This job is no longer available.

At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center.

Developing great technology takes more than talent: it takes amazing people who will go the “extra mile” to achieve unthinkable results. It takes peoples who have passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team



JOB DESCRIPTION: Functional Verification engineer for the CSSE Unified Memory Controller(UMC) IP.

RESPONSIBILITIES: As a functional verification team member, you would:

Provide technical expertise for developing the functional verification strategy of AMD’s next generation Unified Memory Controller(also known as Dram Controller IP);
Understand the architecture of the Dram Controller IP and create the Stimulus, checkers and coverage for the functional block being designed
Maintain and enhance existing verification infrastructure
Develop new test plans, functional coverage points, and test bench components like test-cases, monitors, scoreboards, sequencers, and sequences
AMD uses IP-XACT methodology.
UMC integrates the ddr phy into our IP and also integrates the UMC IP into server and client SOCs.



DAILY ACTIVITIES INCLUDE:

· Looking at the RTL to find functional bugs,

· Working with the RTL team to fix the bugs,

· Reading the AMD Memory Controller MAS(micro-architectural Spec) and Jedec DRAM Guidelines (ddr4/lpddr4/lpddr5//ddr5/NVDIMM-p) and DFI (Dram Phy Interface Spec)

· Developing test plans, functional coverage points, monitors, scoreboards, sequencers, and sequences, which utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved.

The role generally entails a mixture of:

Ownership of a piece of our test bench,
Planning & execution of feature additions and
Bug fixes
debug of regression signatures.
Closing Functional Coverage to zero holes on each Client and Server Variant in area assigned;
Innovating UMC testbench: Improving UMC IP testbench each year (build times, re-use, integration times/flow, automating flows, etc);

REQUIREMENTS:

Requires demonstrated technical expertise in functional verification of complex designs including: test planning, test bench development, stimulus generation, checking, and functional coverage.
Requires strong Object Oriented programming and debug skills.
Significant experience with Verilog and System Verilog, Object Oriented Programming/C++, Perl, and logic simulation is a requirement.
Experience with OVM or UVM is a must.
Must have good communication & Analytical thinking skills
Requires the ability to work independently as well as in a cross-site team environment.
Must have knowledge of entire design process from Design specification, defining architecture, micro-architecture, RTL design and functional verification, Tape-out, and post-Si debug.
Experience with dram controllers, memory models(ddr4, lpddr4, ddr5, lpddr5, hbm), Jedec and/or ddrphy(s) is a plus..
Have hands-on experience in Design/Integration activities.
Some exposure to DFT is a plus.
Should be able to work closely with RTL Designers and SOC Design teams across multiple sites..

EDUCATION:

Master in Computer Engineer or EE with at least 5 years of Functional Verification Experience
or Bachelor in Computer Engineering or EE with at least 8 years working Functional Verification experience in ASIC area (preferably IP Functional Verificaiton)



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Requisition Number: 62725