MTS ASIC / Layout Design Engineer

5 - 7 years experience  •  Semiconductors

Salary depends on experience
Posted on 02/21/18
5 - 7 years experience
Semiconductors
Salary depends on experience
Posted on 02/21/18

Responsibilities:

  • Working with architects to understand features to be implemented and verified
  • Block level test plan creation
  • Block level test bench creation and maintenance
  • Block level design verification test creation (directed and random)
  • Test execution and review to meet functional and code coverage requirements
  • Debugging verification test failures to determine if it is a design or verification test defect, correcting test issues and working with the design team to correct defects
  • Might also be responsible for the creation of C models for a portion of the design
  • Might also be responsible for RTL coding, using Verilog, of modules in the design

 

Requirements

  • Must have a BS degree in Electrical or Computer Engineering (MS degree preferred).
  • Must have 5 years of experienced in ASIC verification.
  • Must be proficient in Verilog, System Verilog, C and C++, OVM/ UVM,  Perl, Unix shell scripting, makefiles and the make utility, and working in Linux and Windows environments
  • Must have ASIC design knowledge and be able to debug Verilog RTL code using simulation tools
  • Must have a good knowledge of Software Engineering and excellent programming skills
  • Must demonstrate strong analytical thinking and problem solving skills with an excellent attention to detail
  • Must have good English hearing, speaking, reading and writing capabilities
  • Must have good teamwork and interpersonal skills
  • Graphics pipeline experience is preferred

 

#LI-PS1

 



Requisition Number: 53221

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