- BS degree in Electrical Engineering or equivalent practical experience.
- 5 years of experience in power management or low power design/methodology.
- Experience with ASIC power analysis methodology.
- MS/PhD degree in Electronics, Computer Engineering or Computer Science, with an emphasis on computer architecture and performance and power analysis.
- Experience with power components, power modeling, power trees, power distribution network and design.
- Experience with low power design techniques (such as multi Vth/power/voltage domain design, clock gating, power gating, Dynamic Voltage Frequency Scaling (DVFS)/AVS, etc).
- Experience in droop detection and mitigation, adaptive clock distribution, aging and process monitors.
- Familiarity with PMIC, SMPS and LDO.
- Knowledge of industry trends and disruptive technologies. Knowledge of the impact of software and architectural design decisions on power and thermal behavior of the system, such as thermal mitigation and scheduling, and cross-layer policy design.
About the job
Google engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another. As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people. We need our engineers to be versatile and passionate totake on new problems as we continue to push technology forward. If you get excited about building new things and working across discipline lines, then our team might be your next career step.
Google's mission is to organize the world's information and make it universally accessible and useful. Our Hardware team researches, designs, and develops new technologies and hardware to make our user's interaction withcomputing faster, more powerful, and seamless. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, our Hardware team is making people's lives better through technology.
- Define System on Chip (SoC) power management (architectural and micro-architectural) details for an SoC that includes functions such as image compute, CPU/GPU, for maximum performance under power and thermal constraints.
- Perform algorithm development, modeling and analysis of power management approaches.
- Identify power optimization techniques applicable at different design levels.
- Produce detailed documents for the proposed implementation or power management block; produce detailed trade-off analysis for engineering reviews and product roadmap decisions.