Mobile SOC Power Management Architect, Consumer Hardware

Google   •  

Mountain View, CA

Industry: Information Services


5 - 7 years

Posted 265 days ago

This job is no longer available.

Google engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another. As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people. We need our engineers to be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and working across discipline lines, then our team might be your next career step.

Google's mission is to organize the world's information and make it universally accessible and useful. Only one thing consistently stands in the way between our users and the world's information - hardware. Our Hardware team researches, designs, and develops new technologies and hardware to make our user's interaction with computing faster, more powerful, and seamless. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, our Hardware team is making people's lives better through technology.


  • Design and optimize CPU/GPU/SOC power management for maximum performance under power and thermal constraints.
  • Perform algorithm development, modeling and analysis of power management approaches. Identify power optimization techniques applicable at different design levels.
  • Model the SOC power for use cases, maintain power roll-up at the chip level.
  • Work with cross-functional teams to produce subsystem and system power projections and improve the power model.
  • Evaluate and optimize different power distribution (voltage rail assignments, regulator assignment, etc.) for a complex SOC.



  • BS degree in Electrical Engineering or equivalent practical experience.
  • 5 years of experience in power management or low power design/methodology.
  • Experience with ASIC power analysis methodology.
  • Experience with low power design techniques (such as multi Vth/power/voltage domain design, clock gating, power gating, Dynamic Voltage Frequency Scaling (DVFS)/AVS, etc.).


  • MS/PhD degree in Electronics or Computer Engineering or Computer Science with an emphasis on computer architecture and performance and power analysis.
  • In depth experience with power components, power modeling, power trees, power distributionnetwork and design.
  • In depth knowledge of impact of software and architectural design decisions on power and thermal behavior of the system such as thermal mitigation and scheduling, cross-layer policy design.
  • Familiarity with power estimation tools such as PT/PTPX, PowerArtist, Power-Pro
  • Familiarity with PMIC, SMPS, LDO.
  • Knowledge of thermal analysis and resistive thermal models and heat transfer analysis.