You will be responsible performing IC layout design and leading a small team of layout designers supporting next generation mixed signal CMOS IC's. This position is responsible for providing leadership of block and chip level layout activities and coordinating layout resources for multiple projects to ensure timely, error free chip tapeouts. Serve as the primary interface to design engineering groups, CAD tools support and CAD systems support groups and maintain close working relationships with internal customers.
- Understand development requirements and develop schedules with project managers and layout leads
- Work with analog leads on block & chip level layout
- Perform hands-on layout tasks as required
- Improve productivity, drive layout consistency & adoption of layout methodologies
- Collaborate with design managers, project managers and design engineers
- Resource allocation & tracking
- Schedule layout reviews
<strongRequired Skills and Qualifications
- Associatedegree in IC Layout or related field and 10+ years industry experience.
- Minimum of 5 years in a Layout Manager or Layout Supervisor role supporting mixed signal, CMOS based products
- Deep understanding of layout tools including Virtuoso, Calibre Physical Verification & OA environment
- Expert-level knowledge of Cadence, Calibre LVS, ERC and DRC.
- Consistent track record of leading IC Layout efforts and history of on time delivery.
<strongPreferred Skills and Qualifications
- BS in Electrical Engineering or Electronics Engineering Technology.