Mixed-Signal Design Engineer

15+ years experience  •  Business Services

Salary depends on experience
Posted on 09/21/17
Austin, TX
15+ years experience
Business Services
Salary depends on experience
Posted on 09/21/17

Mixed-Signal Design Engineer

  • Job Number: 112958879
  • Austin, Texas, United States
  • Posted: 25-Aug-2017
  • Weekly Hours: 40.00

Job Summary

In this role, you will be driving Mixed-Signal design efforts. This will require interfacing with architecture, CAD, timing and logic design teams, with a critical impact on delivering best in class designs. You will be required to lead and carry out micro-architecture specifications, physical designs, design analysis (including circuits, timing, and quality checks), design bring up, and design sustaining.

Key Qualifications

  • The ideal candidate will have
  • 15+ years of Circuit Design experience on Mixed Signal Circuit designs/architectures
  • Ability to comprehend system level requirements of a specific design and drive a micro-architecture spec
  • Experience in some areas of design such as data convertors, high speed SERDES, PLLs, reference circuits, analog circuits, mixed signal design
  • Working Knowledge of Basic SoC Architecture and HDL languages like Verilog/VerilogAMS/VerilogA
  • Working knowledge of AMS simulation tools such as SPECTRE AMS
  • Working knowledge of Extraction and STA methodology and tools
  • Good understanding of Circuit Verification tools like EMIR, Noise, SigEM, clocks etc.
  • Ability to lead a large program involving up to a dozen engineers while interfacing with various parts of the organization such as PD, DV, RTL, SOC, and test


As a Mixed Signal Design Engineer you will be involved with all phases of specification, design, bring up, and characterization of high performance mixed signal designs. Your responsibilities include but are not limited to: Generate block/chip level spec for the architecture. Work with the design and layout team to come up with efficient design. Develop and validate high performance systems using MATLAB, Verilog and SPICE. Lead a team to perform block level verification to close the design to meet timing, area and power constraints. Interface with various teams in the org such as SOC, PD, DV, Test Engineering, Product Engineering, and Platform Engineering/Validation


BSEE / MSEE required.

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