- Planning and execution of external memory interface characterization and system-level validation including blocks such as DLLs and GPIO. Support rates up to 2133 Mbps for DDR3.
- Interact with design and software development groups in device level and board /system validation and characterization.
- FPGA centric reference design development: Architecture, detailed design, coding, bring up, testing, performance measurement/demonstration and delivery for Customers.
- Responsible for Achronix’s external memory IP product development and support.
- Develop Technical notes, design guidelines, interoperability testing for DDR2/3 RLDRAM II and QDR II External memory interface.
- Develop technical notes, design guidelines, interface test reports for various external memory interfaces.
- Support overall product bring-up of external memory Interface hardware and associated hard and soft IP in the FPGA fabric.
- Participation in next generation external memory interface requirements definition and validation.
- Knowledge and familiarity of memory interfaces such as DDR2, DDR3, QDR II and RLDRAM II.
- Verilog/VHDL – RTL coding/simulation and validation in FPGA-based boards.
- Hands on experience in debugging PCBs, using high end scopes compliance testing in a hardware lab and experience in lab automation.
- Strong in technical writing and communication (verbal) skills
- Knowledge of high-speed serial protocols a plus
A minimum of 5 years performing the tasks outlined in job description/responsibilities section.