Lead Static Timing Analysis (STA) Engineer

Encore Semi   •  


8 - 10 years

Posted 304 days ago

This job is no longer available.


In support of the high-demand from our customers, the Physical Design Group is expanding and recruiting new members in the area of Static Timing Analysis and Timing Closure. The focus of this team is to implement complex, high speed, low power SoC designs across multiple application areas.  We partner with the top-tier SoC companies to implement designs from RTL to tapeout, on today’s most complex process technologies, using the latest EDA tools and physical implementation methodologies.

Essential Duties/Responsibilities/Functions/Tasks:

• Run static timing analysis using Cadence Innovus / Tempus on large complex SoCs
• Develop constraints including modeling clock domain crossings
• Analyze STA results and enhance/modify timing constraints to close timing on block and chip level
• Work with physical design team to close timing using MMMC methodology
• Experience with advanced technology nodes required (28nm, 20 nm, 14 nm, 7nm)
• Strong scripting skills are desirable (TCL, Perl, Python)
• Good understanding of physical design flow and how to interact with PD team

Minimum Qualifications:

• 7+ years of STA experience Cadence Tempus or ETS (Encounter Timing System)
• Understanding of MMMC timing in the FinFET nodes (14nm, 7 nm) using Multi VT libraries
• Excellent understanding of constraint generation 
• BSEE required

Preferred Qualifications:

• Cadence timing tool experience
• Understanding of Innovus P&R tool suite is a plus
• Perl coding experience