At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
This is a unique opportunity to join the rapidly growing Product Engineering team in the IP Group at Cadence Design Systems. We are looking for a Lead Product Engineer who will be the main technical interface on Key Customer engagements deploying our advanced high speed PHY IP. This is a hands on technical position. The candidate must have experience successfully integrating and/or designing high speed PHY IP in an SOC and product level environment.
Main Tasks and Responsibilities:
- Main technical interface between R&D team and tier one customer design teams integrating advanced high speed PHY IP.
- Primary technical contact for customer SOC integration and DFT questions.
- Support customer SOC teams from RTL and PHY integration to final GDS, and production ramp.
- Primary technical link between R&D team and Field Application Engineers
- Generate technical specification, data sheets, and application notes.
- Update R&D teams with the latest customer feedback and competitive analysis.
- Support the entire IP product delivery cycle starting at initial presales stages.
- M.S. Electrical/Computer Engineering (or similar degree)
- At least 3 years of experience developing or using high speed PHYs (16Gbps+)
- Experience with PHY wafer probe and ATE testing desired.
- Experience working with USB, SATA, PCIe, or Ethernet protocols.
- Experience in SOC design implementation, from RTL to final GDS, and production ramp.
- Verilog design and static timing close experience.
- Experience with industry standard DFT flows and methodologies.
- Strong Exposure to all major IC implementation, DFT, design, verification, and debug tools.
- Strong debug and problem solving skills
- Familiarity with advanced technology nodes (16nm and below) is a plus
- Must have strong group presentation skills.
We’re doing work that matters. Help us solve what others can’t.