Lead Physical Design Engineer

Encore Semi   •  

Austin, TX

11 - 15 years

Posted 308 days ago

This job is no longer available.


In support of the high-demand from our customers, the Physical Design Group is expanding and recruiting new members in the area of Physical Design implementation including Floorplanning, P&R, Timing Closure, and Physical Verification (DRC/LVS/Antenna). The focus of this team is to implement complex, high speed, low power SoC designs across multiple application areas.  We partner with the top-tier SoC companies to implement designs from RTL to tape-out, on today’s most complex process technologies, using the latest EDA tools and physical implementation methodologies.

Required Qualifications:

• Must have experience in full chip and block level physical design in 28nm, 20nm, 14nm technologies
• Extensive experience with floorplanning and Clock Tree Synthesis (CTS)
• Good knowledge of physical verification tools and methodologies, in particular Calibre
• Good knowledge of static timing analysis (STA) and timing closure
• Ability to use scripting languages to automate process flow
• Work effectively with global team and be self-motivated to solve problems
• Good communication and leadership skills 
• BSEE plus 10 or more years of physical design experience 
• Extensive experience with Cadence, Synopsys and/or Mentor physical design tools

Preferred Qualifications:

• Extensive experience with Cadence Innovus tools and flows
• Team lead experience