Lead Design-for-Test (DFT) Engineer (Cadence tools expert) Email inShare

Encore Semi   •  

Virtual / Travel

8 - 10 years

Posted 307 days ago

This job is no longer available.


In support of the high-demand from our customers, the Physical Design Group is expanding and recruiting new members in the area of Design for Test (DFT). The focus of this team is to implement advanced DFT/DFD functionality in high performance SoCs. The successful candidate will work on deployment of DFT methodologies that reduce test cost, increase production quality and enhance yield. We partner with the top-tier SoC companies to implement designs from RTL to tapeout, on today’s most complex process technologies, using the latest EDA tools and physical implementation methodologies.

Minimum Qualifications:

• Experience with industry DFT methodologies including SCAN, MBIST, JTAG, ATPG, and compression
• Understanding of core-based test methodology and scan isolation
• Knowledge in fault modeling Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, and other advanced DFT models
• Experience with industry DFT tools, some experience with Cadence DFT tools required
• Good scripting skills
• 7+ years of experience of DFT implementation
• BSEE degree required

Preferred Qualifications:

• Extensive use of Cadence DFT tools
• Team lead experience