Maxim Integrated is a highly successful, $2.4 billion company. With offices and manufacturing sites around the world, we design award-winning semiconductors that make the world more integrated. We also know that it’s our people who make us a great company. So we reward bold thinking, teamwork, personal growth, and community involvement. Want to make a difference and be challenged every day? Join us at Maxim Integrated. With analog integration, the possibilities are endless.
Maxim is seeking a senior-level Digital/Mixed Signal Verification/Design Engineer to verify and design integrated circuits and support assigned products through the full product life cycle in the Automotive business unit located in Chandler, AZ. Emphasis will be mainly on verification, though design assignments will also be available on an as-needed basis. Project and/or personnel leadership responsibilities may be assigned to highly qualified and motivated individuals.
Responsibilities may include, but are not limited to:
Definition and Verification of interfaces, state machines, and controlling logic required to implement new products in a wide range of application spaces
RTL digital architecture, design, and problem solving
Development of directed and constrained random test cases in SystemVerilog
Architect, implement, and/or manage complete metric-driven SystemVerilog and UVM verification environments as determined by project complexity
AMS and real number modeling of analog blocks
Digital synthesis, place-and-route supervision, including STA, LEC, GLS, etc. tasks as needed by the project
Project leadership responsibilities
Possible personnel leadership/mentorship roles (for qualified candidates)
BSEE + 6 years or MSEE + 4 years Digital and/or Mixed Signal IC verification/design experience.
Strong written and verbal communication skills.
Strong RTL and general coding, object-oriented programming, and documentation skills.
RTL design for synchronous applications, including multiple clock domains in Silicon (asynchronous design experience a plus).
Strong SystemVerilog fluency in design, simulation, and verification domains.
Extensive experience with a scripting language (Perl, Python, C, etc.)
Experience developing UVM test plans, environments, and test cases.
Demonstrated success in project or block level leadership roles.
Knowledge of and capability to execute the entire digital verification/design process without significant assistance.
Motivation to learn and master the full digital verification and design process (eventually covering all areas of experience listed below).
Maxim is an equal opportunity employer and gives consideration for employment to qualified applicants without regard to race, color, religion, sex, national origin, disability or protected veteran status.
Definition and implementation of custom digital interfaces (I2C, SPI, UART, etc.).
Definition, design, and verification experience with custom state machines and control logic for use with analog circuits such as data converters, mixed signal processing functions, references, linear regulators, DC-DC converters, etc.
Mixed-signal simulation (Cadence AMS), interfacing with analog functions (Verilog-AMS or real number modeling experience a plus).
Verification test plan creation, coverage closure, test case, and regression suite development.
Logic synthesis, interfacing with place & route staff, static timing analysis, logic equivalency checking, etc.
Design for test, scan insertion, ATPG, functional test vectors, etc.
Advanced knowledge of complex IC verification techniques (SystemVerilog/UVM).
Product definition involvement
Technical project management
Mentorship and development of personnel and/or small teams
Experience in introducing products to the market and/or customer support.