MicroVision is the creator of PicoP® scanning technology, an ultra-miniature laser projection and sensing solution based on the laser beam scanning methodology pioneered by the company. The technology is well suited to support a wide array of applications including interactive projection, 3D LiDAR sensing for applications such as advanced driver assistance systems (ADAS), robotics and industrial applications, and Augmented and Virtual Reality (AR/VR). MicroVision is an independently recognized leader for its formidable intellectual property portfolio. The company is based in Redmond, Washington.
MicroVision is seeking an HDL Design Timing Engineer to join the Engineering team.
Essential Duties and Responsibilities:
- Collaborate with cross-functional engineering teams to support development of novel electronic devices leveraging laser beam scanning (LBS) technology.
- Ensure physical design and timing accuracy of high-frequency multi-FPGA development platforms, balancing objectives of FPGA-based system performance with ASIC program readiness.
- Perform timing analysis and timing constraint development at the module and chip level.
- Assist with design partitioning and floor planning activities.
- Develop timing critical interface logic for FPGA/ASIC targets.
- Participate in lab-based hardware testing, troubleshooting, and performance validation.
- Other job duties as assigned.
Required Knowledge, Skills and Abilities:
- Significant experience performing static timing analysis, constraints generation/management, and timing closure.
- Hands on experience in digital logic synthesis and in assessing design decisions based on their impact on timing, power, and area.
- Proficiency in scripting languages, such as Python, Tcl, Make, etc.
- Expertise in industry standard EDA tools including HDL synthesis tools and simulators (Xilinx, Mentor, Cadence, etc)
- Experience implementing HDL designs in native languages (Verilog, VHDL, etc)
- Experience with analog/digital converter interfaces (ADCs, DACs)
- Ability to organize and prioritize work
- Bachelor Science in Electrical Engineering or related field and 5+ years experience or equivalent combination of education and experience.
- Understanding of synthesis, logic equivalence, DFT, BIST, and backend-related tool flows.
- Prior experience completing multiple successful ASIC/IP tape-outs.
- Experience with continuous integration design flows.
- Familiarity with digital signal processing and statistical processing methods.
- Development experience with radar, lidar and/or RF communication systems.
- Experience with Xilinx Vivado and the Ultrascale+ device family.