The employee will work on the physical implementation of blocks from RTL to GDS in advanced FinFet technology nodes (7nm/12nm/14nm/16nm) and below. The employee will also share responsibilities across design and verification. His/her responsibilities will include the following:
- RTL synthesis, writing timing, area, and other relevant constraints.
- Floorplanning, power grid implementation, clock tree synthesis, place and route.
- Parasitic extraction and physical design verification.
- Static timing analysis, and timing closure.
- Lint, design for test, test coverage.
- EM/IR verification and logic equivalence/formal verification.
- Low-power design and power optimization.
- Collaborate with other members of the team to optimize design in context.
- Work with other team members to improve methodologies and flows.
- Support post-silicon product bring-up and debug, timing and power characterization.
- Experience with digital VLSI CMOS circuit design and physical design in advanced FinFet technology nodes.
- Experience with HDLs such as Verilog.
- Experience with industry-standard tools such as Design Compiler, ICC2, PrimeTime, Tetramax, RedHawk, ICV, Caliber LVS/DRC.
- Excellent debugging skills.
- Comfortable programming in a scripting language (e.g., Python or Perl) and writing full programs from scratch (e.g. 5000+ lines of code).
- Familiarity with revision-control systems (e.g., Perforce, git).
- Familiarity with using and/or designing FPGAs is a plus.
- Well organized, punctual, excellent communication skills; ability to operate without direct supervision; ability to collaborate with other team members.
MS in Electrical Engineering with 3-10 years experience.