Responsibilities include strong FPGA design knowledge. Must be capable of RTL design, simulation, physical implementation and verification of complex FPGA modules comprising a mix of custom RTL with hard and soft vendor IP cores within a larger architecture. Must be able to validate compliance to performance constraints, perform static timing analysis and develop functional simulations to ensure proper implementation.
Qualified Candidates will have:
- BSEE, BSCE or equivalent degree
- Minimum 3+ years experience in digital design development, implementation & debug.
- Experience with RTL coding using SystemVerilog, Verilog or VHDL, all are desirable.
- Ability to develop automated self-checking test benches and verify HDL code.
- Hands on experience using Xilinx Vivado design suite.
- Experience with static timing analysis and optimizing logic design for timing closure.
- Experience designing signal processing functions for video and image processing is desirable.
- Excellent communication skills (written and verbal)
- Strong attention to detail, highly organized, computer literate
- Ability to work well in a fast-paced professional office environment