About The Neenah Design Center
Plexus Engineering Solutions’ Center of Excellence for over 35 years, The Neenah Design Center is home to over 200 engineers and designers providing quality, innovative designs to our customers around the World. Residing in East-Central Wisconsin, The Fox Valley Region is one of the largest & fastest growing urban centers in the state, having been recognized as one of the “Best Small Places for Business and Careers” by Forbes.com while also being named one of the Top 10 Best Affordable Places to Live. With a population of more than 230,000, The Fox Valley offers a unique and attractive blend of urban lifestyle and small-town culture with a wide variety of recreational activities for the outdoor enthusiast, all conveniently located only a short drive from Green Bay, Madison, Milwaukee and Chicago.
About the Role
Plexus Engineering Solutions is seeking a skilled Senior FPGA Verification Engineer for defining the verification methodology for complex FPGAs. This person will create verification test plans and test cases, as well as architect and implement test benches to verify FPGA requirements.
Key Job Responsibilities
- Develop engineering/product concepts that are innovative, high-quality, cost-appropriate, and satisfy all stakeholder (customer, manufacturing, material, etc.) needs and requirements throughout the full Product Realization value stream
- Utilize appropriate tools and equipment to perform necessary design work including design creation, design analysis, and design verification
- Support proposal development through the identification of project tasks, durations, interdependencies, risks and assumptions
- Effectively work independently without direction from mentors of functional management
- Directly interface with customer to clearly and concisely communicate technical information
Skills & Abilities
- Demonstrated history of verifying large, complex FPGA designs
- Strong knowledge of revision control concepts and tools (ex. Subversion)
- Ability to author verification plans and test cases
- Working knowledge of coverage driven verification methodology, implementing functional and coverage assertions and working to close coverage
- Ability to perform scripting (ex. Perl, Python, Tcl, Bash)
- Ability to lead a small team of engineers through the FPGA development process, preferred
- Advanced abilities in mentorship and development of others
Education & Experience
- A minimum of a Bachelor’s degree in ElectricalEngineering or Computer Engineering is required for this position
- 6+ years of verifying complex FPGAs using industry standard tools and methodologies is required, 8+ years is preferred.
- Extensive(5+yrs)experiencein the following areas:
- Using SystemVerilog and constrained random verification techniques
- Verification methodology such as UVM or OVM
- Performing simulations using ModelSim or QuestaSim
- Experience working in the Linux environment is preferred
- Familiarity with C++ and RTL Design is preferred
All offers of employment are contingent upon successfully passing a drug screen and upon completion of a confidentiality agreement.