Formal Verification – CAD Engineer
- Job Number: 112979140
- Santa Clara Valley, California, United States
- Posted: Sep. 18, 2017
Formal Verification CAD engineering plays a major role in promoting a reliable work environment for Formal Verification teams. There are many applications within the formal verification arena that need support, such as formal property checking, low power, connectivity checks, sequential equivalence checking (SEC), and coverage. In addition to maintaining and enhancing our Formal Verification flow, you will contribute in developing, maintaining and enhancing our Linting, Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) applications for SoC projects across multiple sites.
- Typically requires at least 5+ years of experience.
- Expertise in Jasper products is highly desirable.
- Experience in Spyglass Lint, DFT and CDC products is a plus.
- Experience in any Reset Domain Crossing tool is a plus.
- Expertise in Verilog and System Verilog is required.
- Expertise in TCL and PERL is required.
- Experience in low power verification is a plus.
- Strong software development background.
- Must have good communication skills, previous customer support is a plus.
- Must be comfortable with co-developing an existing system.
-You will be responsible for developing, maintaining, and enhancing an existing system of executing a formal verification tool. -You will help out with supporting our existing Jasper reset analysis, SEC and formal proofing flows. -You will utilize your debugging experience to debug vendor tool problems and interact with designers/formal verification team to help solve their problems.
MS/BS Degree in technical discipline.