Ethernet Sub-system / Clock-Reset Subsystem Verification Lead in Hillsboro, OR

$150K - $200K(Ladders Estimates)

Intel   •  

Hillsboro, OR 97123

Industry: Telecommunications & Hardware


8 - 10 years

Posted 39 days ago

Job Description

Come and join us! Intel is seeking highly qualified candidates to join our Data Center Group (DCG) as an Ethernet Sub-system/Clock-Reset Subsystem Verification Lead!

The Custom ASIC business is poised for explosive growth in areas such as accelerators for Application processing (AI and media) and Infrastructure (5G, Smart NIC and switches), and this is your chance to help define and drive our success.

Responsibilities will include, but are not limited to:

- Oversees definition, design, verification, and documentation for SoC (System on a Chip) development.

- Determines architecture design, logic design, and system simulation.

- Defines module interfaces/formats for simulation.

- Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs.

- Contributes to the development of multidimensional designs involving the layout of complex integrated circuits.

- Performs all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing.

- Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.

The ideal candidate will have the following skills in addition to the qualifications listed below.

- Proven track record of uncompromising customer orientation to deliver leading-edge silicon products for data centers

- Complex problem solving and decision making with a proven record of results orientation.

- Ability to work effectively with global teams in a variety of geographies.

- Excellent supplier management skills.

- Excellent communication skills with an ability to synthesize complex info into easy to digest form for senior executives.

In this position you will gain invaluable experience which will allow growth and expanded opportunities within this business group as well as future possible opportunities with other business groups within Intel.

The Data Center Group (DCG) drives new products technologies from high-end co-processors for supercomputers to low-energy systems for enterprise and the cloud, as well as solutions for big data and intelligent devices. The group is a worldwide organization that develops the products and technologies that power 9 of every 10 servers sold worldwide.


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Required Qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, or related plus 9 years of industry work experience, or a Master's degree in Electrical Engineering, Computer Engineering, or related plus 6 years of industry work experience, or PhD in Electrical Engineering, Computer Engineering, or related field plus 4 years of industry work experience.

- 9 plus years of proven and successful experience in verification of sub-systems or full-chip for complex SOC/ASIC development programs.

- 9 plus years of hands on experience with developing verification environments for leading edge high performance data center silicon products including Ethernet/ARM SOCs.

- 9 plus years of experience in verification of high performance silicon products for data center products (preferably 56G/112G+) Serdes/MAC sub-systems.

- 9 plus years of experience expert level experience in verifying high-speed interfaces like DDR/HBM/PCI-Express/Serdes/Ethernet MAC

- 9 plus years of experience expert level experience with verification of system level power up/reset sequence/power management for complex SOC's

- 9 plus years of experience creating and maintaining block-level and chip-level test benches

- 9 plus years of experience developing and managing constrained random stimulus generators and assertion checkers

- 9 plus years of experience writing bus functional simulation models

- 9 plus years of experience with the following languages: Verilog, SystemVerilog, Perl, Python, C/C++, etc.

Additional Preferred Qualifications:

- Master's Degree.

- 4 plus years of post-silicon validation experience.

Valid Through: 2019-11-8